1. Field of the Invention
The present invention relates to a still image recording apparatus.
2. Related Background Art
Conventionally, an electric charge storage time of an interline CCD solid state image pickup (PU) device is controlled by two cycles of interval adjustment of a transfer gate in accordance with timings shown in FIG. 3. In FIG. 3, a vertical synchronizing pulse (a) determines an image transfer timing of an overall image PU system. In a solid state image PU device such as an interline transfer CCD solid state image PU device independently having a photoelectric converter and a transfer register (including a vertical transfer unit and a horizontal transfer unit), transfer of an image signal from the photoelectric converter to the transfer register is performed by a read pulse (b), and the read pulse is defined by a position of the vertical synchronizing pulse. This is because timings and the like of various pulses required for image signal processing are synchronized with a synchronizing pulse of the system. Since a time interval T.sub.7 from a reset pulse (c) to the read pulse (b) of the photoelectric converter corresponds to an exposure time (electric charge storage time), the position of the reset pulse (c) is not arbitrary. For this reason, a delay of a maximum of one vertical synchronizing pulse cycle (one field period) may be generated during a time interval from a time at which a trigger pulse (d) is input in response to an operation of a release button to a time at which the reset pulse (c) is output. The delay time Td changes case by case.
As described above, in a conventional driver, an indefinite delay time is generated in a time interval from a time at which a release button is depressed to a time at which electronic shutter operation is actually performed. Therefore, an instantaneous event cannot be precisely photographed.